IBIS Macromodel Task Group

Meeting date: 19 August 2008

Members (asterisk for those attending):
  Ambrish Varma, Cadence Design Systems
  Anders Ekholm, Ericsson
* Arpad Muranyi, Mentor Graphics Corp.
  Barry Katz, SiSoft
* Bob Ross, Teraspeed Consulting Group
  Brad Brim, Sigrity
  Brad Griffin, Cadence Design Systems
  David Banas, Xilinx
  Donald Telian, consultant
  Doug White, Cisco Systems
  Essaid Bensoudane, ST Microelectronics
  Fangyi Rao, Agilent
  Ganesh Narayanaswamy, ST Micro
  Gang Kang, Sigrity
  Hemant Shah, Cadence Design Systems
  Ian Dodd, Agilent
  Joe Abler, IBM
* John Angulo, Mentor Graphics
  John Shields, Mentor Graphics
  Ken Willis, Cadence Design Systems
  Kumar
  Lance Wang, Cadence Design Systems
  Luis Boluna, Cisco Systems
* Michael Mirmak, Intel Corp.
  Mike LaBonte, Cisco Systems
  Mike Steinberger, SiSoft
  Mustansir Fanaswalla, Xilinx
  Patrick O'Halloran, Tiburon Design Automation
  Paul Fernando, NCSU
* Pavani Jella, TI
  Radek Biernacki, Agilent (EESof)
  Randy Wolff, Micron Technology
  Ray Comeau, Cadence Design Systems
  Richard Mellitz, Intel
  Richard Ward, Texas Instruments
  Sam Chitwood, Sigrity
  Sanjeev Gupta, Agilent
  Shangli Wu, Cadence Design Systems
  Sid Singh, Extreme Networks
  Stephen Scearce, Cisco Systems
  Steve Pytel, Ansoft
  Syed Huq, Cisco Systems
  Syed Sadeghi, ST Micro
  Terry Jernberg, Cadence Design Systems
* Todd Westerhoff, SiSoft
  Vikas Gupta, Xilinx
  Vuk Borich, Agilent
* Walter Katz, SiSoft
  Zhen Mu, Cadence Design Systems
---------------------------------------------------------------------
Opens:
======

Walter:  The whole purpose of EMD was to remove all internal
         circuit information from this file and put it into subcircuit
         (bristles only).

   Bob:  What is the definition of a "bristle"?
   Walter: Any connection point to which external connections are made.
           May include package, connector, oscilloscope probe, etc...
           Separate question is where exactly that point is for through
           hole vias.
   Todd: The term is overloaded, let's not use three different terms
         (port, terminal, bristle) pick one term for clarity.  Several
         participants favored "terminal".
   Discussion on extended net, electrical net, cad net
   Arpad: Let's talk about the fundamental question in the open
   Mike M.: We have had genereralized netlisting formats, now we are
            talking about "extended net" format specific to post layout
            Duality between pre layout vs. post layout database
   Walter:  EMD is manufacturing related, for module design to represent
            something that is physically manufactured
   Todd:    It is not limited to that, is it?
   Walter:  It is not.


--------------------------
Call for patent disclosure:

- No one declared a patent.

-------------
Review of ARs:


Todd and Michael M:  Contact Synopsys about HSPICE legal issues
- A draft is almost ready to be sent to Synopsys, will be finalized
  and sent today.

Arpad:  Post last weeks material to IBIS-ATM's web site
        - done on 8/15/2008

        Prepare an IBIS-EBD improvement list
        - in progress


Old ARs:

- David Banas: Report Xilinx position on LTI assumption for SerDes
  - no update

- Arpad:  Write parameter passing syntax proposal (BIRD draft)
          for *-AMS models in IBIS that is consistent with the
          parameter passing syntax of the AMI models
          - not done

- TBD:    Propose a parameter passing syntax for the SPICE
          [External ...] also?

- Arpad:  Review the documentation (annotation) in the macro libraries.
          - deferred until a demand arises or we have nothing else to do


-------------
New Discussion:

Arpad proceded with explaining the proposal that was posted to the
IBIS-ATM web site on 8/15/2008.
Walter considers the proposal unnecessarily complicated and doesn't
agree with having any netlisting capability in the EMD specification.
Arpad feels that removing the netlisting to the subcircuits only defers
the problem that will have to be solved sooner or later.
Walter disagrees, becuase he feels that the HSPICE subset language would
solve anyone's netlisting needs.
The discussion kept returning to the original "fundamental question" 
brought up in the opens by Walter: what do we want to cover in this
specification.
Walter suggested that he would discuss his "original" proposal from
April so we would all be on the same page again.
Now that it has been introduced, 
Arpad suggested that people look at
his proposal in more detail and provide feedback on it on the reflector
or in next week's meeting.


Next meeting: 26 August 2008 12:00pm PT

-----------